The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure containing vertical transistors having optimized source/drain extension regions and a method of forming the same.
Conventional vertical transistors are devices where the source-drain current flows in a direction normal to the substrate surface. In such devices, a vertical semiconductor pillar defines the channel with the source and drain located at opposing ends of the semiconductor pillar. One advantage of a vertical transistor is that the channel length is not defined by lithography, but by methods such as epitaxy or layer deposition, which enable precise dimensional control. As such, vertical transistors are an attractive option for technology scaling for 5 nm and beyond.
One difficult challenge in forming vertical transistors is the variation in gate length, spacer thickness and source/drain extension doping profile due to the integration challenges posed by the vertical orientation of the transistors. There is thus a need for providing vertical transistors in which the variation in gate length, spacer thickness and source/drain extension doping profile are well controlled. Notably, an optimized source/drain extension region can provide performance benefits to semiconductor structures containing vertical transistors.